Generalized Delay Optimization of Resistive Interconnections
نویسنده
چکیده
Abshrrct: Resistance of VLSI interconnections has become significant due to large die sizes and sub-mkm geometries in high performance designs. Previous studies have proposed optimal repeater schemes wing slmple buffers for delay optimization of the interconnection. This paper proposes a more general approach that handles arbitrary logic gates as well as buffers. The methodology is based on an extension of the concept of logical effort. The optimization yields proper spacing of the given logk gates, additional repeaters (buffers) required for a given RC line, and sizing of all the gates This approach is applicable to many deslgn situations where existing logic gates must be considered in the overall repeater scheme.
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